Instruction set architecture to control instruction fetch on pipelined processors

Instruction fetching is usually the default action related to the program counter, and it is affected by the execution of a branch instruction. However, the processor does not know about the timing of a branch until it fetches a branch instruction, and it must start processing the branch just after fetching a branch instruction. Hence this situation causes control hazards. To solve this problem, the authors are engaged in studies on the control of instruction fetching and have developed a new mechanism as the first solution. In this mechanism, instructions to control instruction fetching are inserted into programs. The processor can identify these without decoding, and it processes in parallel with the other instructions. The paper describes the instruction set architecture of this mechanism, and describes its performance evaluation using a software simulator