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This paper describes a new method for designing digital controller and their FPGA based realization schemes. The design method is based on time domain response to meet three different time domain specifications settling time, peak overshoot/rise time and closed loop gain ensuring minimal ITAE. This design method follows Graham Lathrop optimal polynomials (GL Polynomials) with an introduction of Left Hand Side zero (LHS Zero). The same design method to be applicable for any system from 2nd to 6th order. Simulation results of tests for robustness and specifications change also featured in this paper.