Cart (Loading....) | Create Account
Close category search window
 

Design and performance analysis of shift register-based ATM switch

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Elguibaly, F. ; Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada ; Agarval, S.

We present a modified design of the shift register-based ATM switch introduced by El-Guibaly, Sabaa and Shpak (see IEEE ETACOM '96, p.24-7, 1996). The switch design has been modified to perform connection admission control (signalling) and management (OAM) functions. This switch overcomes the HOL and low throughput problems and supports QOS and multicasting functions. The internal details of each module of the switch architecture are presented. Also, a performance analysis of the switch is done to find the cell loss probability and throughput

Published in:

Communications, Computers and Signal Processing, 1997. 10 Years PACRIM 1987-1997 - Networking the Pacific Rim. 1997 IEEE Pacific Rim Conference on  (Volume:1 )

Date of Conference:

20-22 Aug 1997

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.