Skip to Main Content
Wire shaping for delay/power minimization has been extensively studied. Due to the perceived high design and manufacturing costs for using nonregular wire shapes, wire shaping is generally considered to be impractical. In this paper, we present a practical wire shaping method to reduce power consumption of interconnect. Nonregular wire shapes are directly implemented on silicon wafer instead of in GDSII during design. We present novel enhancements to existing optical proximity correction (OPC) technology to accurately print nonregular wire shapes. Experimental results show that the post-OPC mask complexities of uniform wire and nonregular wire are comparable. With minimal impact on the design and manufacturing flows and minimal additional design and manufacturing costs, we demonstrate that wire shaping can help to obtain substantial reduction of interconnect dynamic power without affecting timing closure. Our wire shaping methodology is an excellent example of Manufacturing for Design.