Cart (Loading....) | Create Account
Close category search window

Stochastic Modeling-Based Variability Analysis of On-Chip Interconnects

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
6 Author(s)

In this paper, a novel stochastic modeling strategy is constructed that allows assessment of the parameter variability effects induced by the manufacturing process of on-chip interconnects. The strategy adopts a three-step approach. First, a very accurate electromagnetic modeling technique yields the per unit length (p.u.l.) transmission line parameters of the on-chip interconnect structures. Second, parameterized macromodels of these p.u.l. parameters are constructed. Third, a stochastic Galerkin method is implemented to solve the pertinent stochastic telegrapher's equations. The new methodology is illustrated with meaningful design examples, demonstrating its accuracy and efficiency. Improvements and advantages with respect to the state-of-the-art are clearly highlighted.

Published in:

Components, Packaging and Manufacturing Technology, IEEE Transactions on  (Volume:2 ,  Issue: 7 )

Date of Publication:

July 2012

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.