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For CMOS technology, the increase of interconnects metal density is responsible for heterogeneous mechanical stress fields in active regions of silicon. Coupled mechanical–electrical measurements are performed to evaluate the impact of stress at circuit and device levels. This mismatch originated by interconnects metal lines stress is measured through the use of piezoresistive test structures. Local mechanical stress can thus be monitored in a simple process control compatible approach.
Date of Publication: Nov. 2012