Design of CMOS Power Amplifiers

This paper describes the key technology and circuit design issues facing the design of an efficient linear RF CMOS power amplifier for modern communication standards incorporating high peak-to-average ratio signals. We show that most important limitations arise from the limited breakdown voltage of nanoscale CMOS devices and the large back-off requirements to achieve the required linearity, both of which result in poor average efficiency. Two fundamentally different approaches to tackle these problems are presented along with silicon prototype measurements. In the first approach, transformer power combining and bias-point optimization are used to increase the output power and linearity of the “analog” amplifier. In the second approach, a mixed-signal “digital” polar architecture is employed, wherein the amplitude modulation is formed through an RF DAC structure.