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A triple-mode class-AB balanced linear power amplifier (PA) is realized in standard 0.18-μm CMOS technology. For the average efficiency enhancement, the triple-mode operation realizes a switched-quadrature coupler with a balanced topology to achieve robust load insensitivity. The PA and RF switches uniquely utilize the isolation port of the switched-quadrature coupler as a signal path in a low-power (LP) mode of operation, and the incorporated output matching network satisfies the |Γ| = 1 condition from the quadrature coupler in the LP mode while providing the necessary load-pull impedance from the PA output side in the high-power (HP) mode. To obtain low loss and high quality factor ( Q) of the passive output-combining network, a transformer-based quadrature coupler is implemented using a silicon-based integrated passive device process. With a 3.4-V power supply, the PA transmits a maximum output power of 28.4 dBm with 40.7% of power-added efficiency (PAE) and linear output power up to 26.6 dBm with 35% of the PAE using a 3-GPP WCDMA modulated signal. With the triple-mode operation, a PAE at 16 dBm is enhanced from 11.1% to 17%, and 47 mA of quiescent current is saved. The PA also shows robust operation under 2.5:1 of VSWR condition, achieving 1 dB of the gain variation and less than 3.9 dB of ACLR variation. This work demonstrates the potential of a highly efficient CMOS PA for WCDMA applications.