An architecture and sensor bus interface for use in generic bus-organized sensor-driven process control systems where high accuracy and high reliability are important are presented. The organization permits 12-b digital sensor data to be communicated to the host processor over bidirectional parallel or serial data buses which include parity checking. Remote testing of the sensor can be implemented along with PROM-based digital compensation of primary and cross-parameter sensitivities. The sensor bus interface is microprocessor controlled, has been implemented using discrete commercial components, and has been designed and simulated in monolithic form. Designs using 3-μm single-metal double-poly and 1-μm double-metal single-poly CMOS technologies are contrasted. Monolithic node integration appears well within the range of current technology, with power levels of less than 75 mW and die areas below 40 mm2. The organization makes sensor interrogations appear much like the memory accesses, yielding very fast response times to the host
Published in:
Semiconductor Manufacturing, IEEE Transactions on
(Volume:3
,
Issue:
4
)
Date of Publication: Nov 1990