An automated design flow framework for delay-insensitive asynchronous circuits

This paper introduces a design flow framework for the Multi-Threshold NULL Convention Logic (MTNCL) circuits, which addresses several optimization problems in the existing flow in order to generate designs with enhanced performance. One problem is buffering feedback loops where searching for the optimal gate replacement is difficult due to interdependencies. Another problem is buffering the MTNCL sleep signal tree which requires certain degrees of prediction while the gate selection is not yet certain. Optimization is achieved by adhering to a specific timing constraint throughout the design utilizing a set of appropriately sized gates. A custom tool has been developed for resolving these issues and automates the process of gate replacement and buffering. The tool combines an iterative approach to gate replacement and a method for inserting starting points in buffering feedback loops. The sleep signal tree is processed using a similar approach. This flow has been successfully applied to a number of test circuits.