Referenced Items are not available for this document.
The AC defect level and yield loss after test for both logic and random-access memory (RAM) semiconductor chips is considered. Computation of chip AC defect level and yield loss, after test, is dependent upon the availability of statistical information regarding the behavior of the chip's delay and of the test error. This statistical information can either be derived from manufacturing process parameters or measured by a tester. The tester accuracy and the test coverage in computing the AC defect level and yield loss are taken into account
Published in:
Semiconductor Manufacturing, IEEE Transactions on
(Volume:3
,
Issue:
4
)
Date of Publication: Nov 1990
- Page(s):
- 195 - 205
- ISSN :
- 0894-6507
- INSPEC Accession Number:
- 3850420
- Digital Object Identifier :
- 10.1109/66.61969
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Nov 1990
- Sponsored by :
- IEEE Components, Packaging and Manufacturing Technology Society
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