Close category search window
 

A hardware acceleration of a real time video processing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Touil, L. ; Lab. EμE, Univ. of Monastir, Monastir, Tunisia ; Ben Abdelali, A. ; Abdelatif, M.

This paper presents a method based on Edge histogram descriptor to accelerate shot cut detector algorithm for real-time applications. In fact, before any content-based manipulations, the hierarchical structure of video must be determined and software pure solution is not suitable for this application due of constraints imposed by this algorithm. In this context we have used a Field Programmable Gate Array (FPGA) integrated architecture to accelerate this treatment.

Published in:
Electrotechnical Conference (MELECON), 2012 16th IEEE Mediterranean

Date of Conference: 25-28 March 2012

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.