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The scaling of key analog properties of CMOS technology under low-voltage conditions, in weak and moderate inversion, is investigated with emphasis on temperature behavior. Design parameters, such as weak inversion slope factor, threshold voltage, mobility, transconductance to current ratio, DIBL, and intrinsic gain, are examined with respect to bias conditions, geometry and temperature. Guidelines are provided to analog designers for the estimation of the variation of fundamental analog design parameters versus temperature. Measured data from NMOS and PMOS transistors of an advanced CMOS technology are provided.