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Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm

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2 Author(s)
Yu-Chi Tsao ; Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA ; Ken Choi

Based on fast FIR algorithms (FFAs), this brief proposes new parallel FIR filter architectures, which are beneficial to symmetric convolutions of odd length in terms of the hardware cost. The proposed parallel FIR architectures exploit the inherent nature of symmetric coefficients reducing half the number of multipliers in the subfilter section at the expense of increase in adders in preprocessing and postprocessing blocks. Exchanging multipliers with adders is advantageous because adders weigh less than multipliers in terms of silicon area, and in addition, the overhead from the increase in adders in preprocessing and postprocessing blocks stay fixed, not increasing along with the length of the FIR filter, whereas the number of reduced multipliers increases along with the length of the FIR filter. For example, for a three-parallel 81-tap filter, the proposed structure saves 26 multipliers at the expense of five adders, whereas for a three-parallel 591-tap filter, the proposed structure saves 196 multipliers at the expense of five adders still. Overall, the proposed parallel FIR structures can lead to significant hardware savings for symmetric convolution in odd length from the existing FFA parallel FIR filter, particularly when the length of the filter is large.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:59 ,  Issue: 6 )

Date of Publication:

June 2012

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