By Topic

A 1-V 15-Bit Audio \Delta \Sigma -ADC in 0.18 \mu m CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Liyuan Liu ; Department of Electronic Engineering, Tsinghua University, Beijing, China ; Dongmei Li ; Liangdong Chen ; Yafei Ye
more authors

In this paper a 1-V supply, 15-bit ΔΣ ADC design for audio applications is presented. The second order CIFB ΔΣ modulator with a 3-bit internal quantizer is adopted. The design of noise transfer function (NTF) is discussed from the viewpoint of mitigating the quantization noise mixture effect. A single-capacitor summing circuit is proposed which eliminates additional amplification or deliberate reference scaling. Nonideal effect due to parasitic capacitance is discussed. With proper modulator architecture, the design of building blocks is relaxed. Low gain amplifier with high power efficiency can be adopted which saves power. The decimator is implemented with cascade subfilters. Time multiplexing of arithmetic resources is employed for low hardware cost. Fabricated in 0.18 μm CMOS, the prototype ADC achieves 91.3 dB peak SNDR with 16 kHz. The modulator dissipates 190 μW and the decimator consumes 170 μW. The core area of the ADC is 0.5 mm2. The modulator occupies 0.3 mm2 and the decimator occupies 0.2 mm2.

Published in:

IEEE Transactions on Circuits and Systems I: Regular Papers  (Volume:59 ,  Issue: 5 )