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Memory array testing through a scannable configuration

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2 Author(s)
Yano, S. ; 1st Comput. Oper. Unit, NEC Corp., Tokyo, Japan ; Ishiura, N.

We have previously proposed a scannable memory configuration which is useful in testing logic blocks around memory arrays. In this paper, from a viewpoint of memory testing, we investigate the testability of the scannable memory configuration and propose a memory array test using the scan path. It is shown that we can detect (1) all stuck-at-faults in memory cells, (2) all stuck-at-faults in address decoders, (3) all stuck-at faults in read/write logic, (4) static, dynamic and 2-coupling faults between memory cells of adjacent words, and (5) static coupling faults between memory cells in the same word. The test can be accomplished simply by comparing scan-in data and scan-out data. The test vector is 20×m+s bit long, where m is the number of words of the memory array under test and s is the total scan path length

Published in:

Memory Technology, Design and Testing, 1997. Proceedings., International Workshop on

Date of Conference:

11-12 Aug 1997