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Use of selective precharge for low-power on the match lines of content-addressable memories

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2 Author(s)
Zukowski, C.A. ; Dept. of Electr. Eng., Columbia Univ., New York, NY, USA ; Shao-Yi Wang

In a CMOS content-addressable memory (CAM), a large amount of energy is generally expended charging and discharging most of the match lines on most cycles. In this paper we explore the use of selective precharge to significantly reduce this problem. The comparator/memory array is partitioned such that a small subset does a portion of each comparison calculation first, and each comparator in the main part of the array is only activated if still needed afterwards. It is shown that such an approach does not necessarily increase the cycle time, but it does affect the timing within a cycle. Estimates are given for the optimal partitioning and the resulting energy savings

Published in:

Memory Technology, Design and Testing, 1997. Proceedings., International Workshop on

Date of Conference:

11-12 Aug 1997