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An analysis of (linked) address decoder faults

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2 Author(s)
van de Goor, A.J. ; Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands ; Gaydadjiev, G.N.

The complexity of memory tests arises when linked faults are taken into consideration. Usually only the class of linked faults in the memory cell array have been taken into consideration, while the class of linked faults involving address decoder faults has been ignored. This paper gives an overview of the most important and commonly used fault models including the disturb fault model. It derives a set of conditions march tests have to satisfy in order to detect address decoder faults (AFs) when they are not linked; these conditions are shown to be dependent on the memory technology (SRAM and DRAM). Next, a set of conditions for march tests are derived to detect linked AFs (linked with other AFs or linked with faults in the memory cell array). The paper concludes with the analysis of a set of well-known march tests for the fault coverage of unlinked and linked AFs. Many of the widely used tests are shown not to be able to detect all (linked) AFs

Published in:

Memory Technology, Design and Testing, 1997. Proceedings., International Workshop on

Date of Conference:

11-12 Aug 1997