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A surface potential-based model for embedded flash memory cells has been developed with the purpose of providing a comprehensive physical understanding of the device operation suitable for performance optimization in memory circuit design. An accurate validation methodology takes into account charge balance effects on the isolated floating gate node and parasitic couplings inside and between the memory cells. The compact model supports DC, AC and transient analyses, including program/erase bias scalability, drain disturb and memory endurance degradation models due to oxide aging. After validation, the model has been applied to parametric analysis and used to evaluate critical trade-offs in memory design.
Date of Conference: 6-7 March 2012