By Topic

Strained silicon nanowire array MOSFETs with high-k/metal gate stack

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Richter, S. ; Peter-Grunberg-Inst. (PGI 9-IT), Forschungszentrum Julich, Julich, Germany ; Trellenkamp, S. ; Schmidt, M. ; Schafer, A.
more authors

This paper presents experimental results on metal oxide semiconductor field-effect transistors (MOSFETs) featuring an array of 1000 trigated uniaxially strained nanowires with a cross-sections of 15 × 15 nm2 in combination with a HfO2/TiN gate stack. The high uniaxial strain along the wires reduces the band gap energy by approximately 140 meV and enhances the electron mobility. Ideal inverse subthreshold slopes of n- and p-channel devices of 60 (62) mV/dec at room temperature and Ion/Ioff ratios up to 1010 were obtained.

Published in:

Ultimate Integration on Silicon (ULIS), 2012 13th International Conference on

Date of Conference:

6-7 March 2012