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Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width

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17 Author(s)
Coquand, R. ; CEA-LETI, MINATEC, Grenoble, France ; Barraud, S. ; Casse, M. ; Leroux, P.
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In this paper, Tri-Gate Nanowire (TGNW) FETs with high-k/metal gate are studied as an alternative way to planar devices for the future CMOS technological nodes (14 nm and beyond). The influence of Si film thickness (H) and nanowire width (W) on electrical performances of long- and short-channel devices are presented and discussed. We show that the transport properties in our TGNW are fully governed by the additive contributions of the (100) top surface and (110) sidewalls. As compared to wide planar devices, the improvement of electrostatic integrity (SS and DIBL) of scaled down TGNW FET is clearly demonstrated.

Published in:

Ultimate Integration on Silicon (ULIS), 2012 13th International Conference on

Date of Conference:

6-7 March 2012

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