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A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps

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3 Author(s)
Ping Lu ; Dept. of Electr. & Inf. Technol., Lund Univ., Lund, Sweden ; Liscidini, A. ; Andreani, P.

Two gated ring oscillators (GROs) act as the delay lines in an improved Vernier time-to-digital converter (TDC), where the already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been implemented in a 90 nm CMOS process and consumes 3 mA from 1.2 V when operating at 25 MHz. The native Vernier resolution of the TDC is 5.8 ps, while the total noise integrated over a bandwidth of 800 kHz yields an equivalent TDC resolution of 3.2 ps.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:47 ,  Issue: 7 )