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We present a shared implementation of a radix-10 and radix-16 fixed-point digit-recurrence algorithm for division operation using limited-precision multipliers, adders, and table-lookups. We discuss the proposed algorithm, its design, and its ASIC implementation using a standard cell library. We present the cost and delay characteristics for precisions of 7 (single-precision), 14 (double-precision) decimal digits, and single and double precision for radix-16. The proposed scheme uses short (2-3 digit-wide) operators which leads to compact modules, reduced interconnections and has an advantage at the layout level as well as in power optimization.