By Topic

Efficient FPGA implementation of a High throughput systolic array QR-decomposition algorithm

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Abels, M. ; Inst. of Electrodynamics & Microelectron. (ITEM), Univ. of Bremen, Bremen, Germany ; Wiegand, T. ; Paul, S.

Due to the Multiple Input Multiple Output technology, applied in wireless communication, where a transceiver has to deal with multidimensional channels, the QR-decomposition is an often used preprocessing algorithm, especially for the design of iterative tree search detection algorithms. In this paper we introduce an efficient FPGA implementation of a QR-decomposition algorithm, which is designed for a MIMO detector developed in view of the Long Term Evolution (LTE). The proposed architecture is based on a line-by-line systolic array structure and reaches the peak matrix throughput, which is required to achieve the defined LTE peak data rate of a 2 × 2 MIMO constellation using a 20 MHz transmission bandwidth. In this paper we describe the architecture and FPGA implementation of the algorithm in detail and show the performance results of a Xilinx Virtex IV realization.

Published in:

Signals, Systems and Computers (ASILOMAR), 2011 Conference Record of the Forty Fifth Asilomar Conference on

Date of Conference:

6-9 Nov. 2011