By Topic

A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

19 Author(s)
Hyun-Woo Lee ; Hynix Semicond. Inc., Icheon, South Korea ; Hoon Choi ; Beom-Ju Shin ; Kyung-Hoon Kim
more authors

The digital delay-locked loop (DLL) with racing mode and the countered column address strobe (CAS) latency controller are proposed in this paper. The dual-DLL architecture with racing operation is adopted to achieve low power consumption, low jitter, fast locking, wide range of locking, and stuck-free control. The merged dual coarse delay line (MDCDL) reduces the dynamic power consumption of a variable delay line by 30% by sharing a part of the delay line path in DLL. In addition, jitter is reduced by 45 ps in the 1066-DDR3 operating mode by MDCDL. The proposed DLL utilizes an or-and functioned duty cycle corrector (or-and DCC), which consumes 15% of DLL's power, 0.915 pJ/Hz at tCK=1.5 ns and VDD=1.575 V. The countered CAS latency controller (CCLC) saves IDD3N current because it does not need a DLL clock and does not need to be activated for IDD3N (active non-power down) state. The DLL clock is enabled and CCLC is activated only when the read command is issued. This operation condition saves the IDD3N current by 60% with the proposed DLL. The proposed DLL is employed in 128 M×8 DDR3 SDRAM and 64 M×16 DDR3 SDRAM. The former and the latter are fabricated by 5×nm and by 4× nm DRAM process technology, respectively. Experimental results show that ±10% duty error of the external clock can be corrected to within ±2% duty error in less than 512 cycles of locking time under 1.5 ns of tCK. The proposed DLL and CCLC can operate above 1.0-GHz operating frequency at 1.2 V in 5× nm DDR3 SDRAM and at 1.0 V in 4× nm DDR3 SDRAM, respectively. The proposed DLL fabricated with 4× nm technology consumes 6.1 pJ/Hz at 1.575 V.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:47 ,  Issue: 6 )