Skip to Main Content
Chip surface topography after chemical-mechanical polishing (CMP) process is greatly influenced by the layout geometric characteristics, such as line width and line space. In order to improve surface topography, dummy fills are often inserted between interconnects. However, this will increase coupling capacitances between interconnects and deteriorates the timing and signal integrity of the chip. In this paper, one flow to acquire optimal dummy fill modes is proposed for both better planarity and less capacitance increment in specific process. As an example of using this flow, we designed test patterns with different fill modes and measured their surface topography and coupling capacitances after the CMP process. Experiment results are displayed and analyzed, and fill guidelines for both better planarity and less coupling capacitance are proposed based on the results. A possible optimal fill mode is also acquired based on the guidelines. In our flow, only one test run is needed in each process, and then all the products run in this process can use these optimal fill modes.