Skip to Main Content
The design optimization for digital circuits built with gate-all-around silicon nanowire transistors (SNWTs) is discussed in details. Based on the verified multiwire SNWT compact model with accurate parasitic capacitance and resistance modeling, the design consideration of SNWT digital circuits (SNWTCs) at a 16-nm technology node, such as the SNWT ring oscillator (SNWT-RO), is discussed with the optimization of key process and layout parameters in the multiwire SNWT. In order to reduce the parasitic components of SNWTs and improve SNWTCs' performance (including delay, power, and layout area), process (including nanowire diameter and other related parameters) and layout parameters (including wire number per transistor and footprint width of SNWTs) should be carefully designed. Through design optimization, the total capacitance and parasitic resistance of the SNWT can be reduced by over 80% compared with nonoptimized parasitic components, which leads to more than 90% reduction of circuit-level delay and power. Furthermore, the design optimization is carried out for power-driven design and area-driven design, respectively. For each case, the SNWT-RO with fan-out of 1 loading and 4 loading is optimized with variable power supply voltage for optimization. The optimized layout parameters for power-driven design and area-driven design are obtained, which can provide useful guidelines for SNWTC design.