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Use of queueing network and trace-driven simulation techniques in PowerPC processor and system performance trade-off studies

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2 Author(s)
Kumar, A. ; Somerset Design Center, Motorola Inc., Austin, TX, USA ; Waldecker, B.

Presents the methodology used and the results obtained in studying design trade-offs for the PowerPC family of processors and system designs using these processors. Specifically, the effects of various cache hierarchies and multiprocessor designs on system performance are examined. Issues dealt with include the performance speedup for different multiprocessor configurations and memory subsystem designs when executing various workloads. Four generic types of workloads were studied. They are defined such that most actual applications should fit into one of the four categories. Results obtained show that system performance is sensitive to the access distance of L2 and L3 caches for many cache sizes and workloads. Required versus available bus bandwidth was examined and found to not be a problem for the systems and workloads under consideration

Published in:

Rapid System Prototyping, 1997. Shortening the Path from Specification to Prototype. Proceedings., 8th IEEE International Workshop on

Date of Conference:

24-26 Jun 1997