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Experimental thermal resistance evaluation of a three-dimensional (3D) chip stack, including the transient measurements

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7 Author(s)
Matsumoto, K. ; ASET (Assoc. of Super-Adv. Electron. Technol.), Yamato, Japan ; Ibaraki, S. ; Sueoka, K. ; Sakuma, K.
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For the thermal management of three-dimensional (3D) chip stack, its thermal resistance needs to be clearly understood. In this study, 3D stacked test chips are fabricated, which are implemented with PN junction diodes for temperature sensors and diffused resistors for heating. At SemiTherm2011, the equivalent thermal conductivity of the interconnection, including BEOL (Back-End-Of-the-Line, wiring layer) is experimentally obtained to be 1.6W/mC and this time, we measure the thermal effect of Cu TSVs and it is experimentally supported that as the Cu TSV area ratio increases, the thermal conductivity of chip with TSVs in the vertical direction increases, on the contrary, that in the horizontal direction decreases. Also, the transient thermal measurement is performed and its result is compared with steady state measurement result. Further, the thermal capacitance measurement of 3D stacked test chip with hot spot heating is performed, which is essential to determine the transient thermal performance of 3D chip stack.

Published in:

Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM), 2012 28th Annual IEEE

Date of Conference:

18-22 March 2012