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Low-power dissipation using FPGA architecture

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2 Author(s)
Muthusamy, S.P.B. ; Dept. of ECE, RVS Fac. of Eng., Coimbatore, India ; Subramaniam, V.

Power optimization is the process of generating the best design in digital VLSI circuits without violating design specifications. In this paper, the existing FPGA routing switch is compared with the proposed low-power FPGA routing circuitry. The experimental results show that the power dissipation in the proposed technique is less than the existing FPGA design.

Published in:

Devices, Circuits and Systems (ICDCS), 2012 International Conference on

Date of Conference:

15-16 March 2012

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