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A 10-b 320-MS/s Stage-Gain-Error Self-Calibration Pipeline ADC

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5 Author(s)
Chien-Jian Tseng ; Dept. of Electr. Eng. & Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Hung-Wei Chen ; Wei-Ting Shen ; Wei-Chih Cheng
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A 10-b 320-MS/s pipeline analog-to-digital converter (ADC) with low dc gain opamps, as low as 30.6 dB based on simulations, in its multiplying digital-to-analog converters (MDACs) is presented. A foreground self-calibration technique is proposed to reduce stage gain error by adjusting feedback factor with a calibration capacitor array. The prototype in 90-nm low-power CMOS technology achieves conversion rate of 320 MS/s with peak SFDR and SNDR of 66.7 and 54.2 dB, respectively. The total power dissipation is 42 mW, and it occupies an active chip area of 0.21 mm2 including the calibration circuit. It results in a figure-of-merit (FOM) of 442 fJ/conversion-step. Only 168 clock cycles are used, and no external precise reference sources are needed for the calibration.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:47 ,  Issue: 6 )

Date of Publication:

June 2012

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