By Topic

Accelerating multiple alignment on FPGA with a high-level hardware description language

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Oleg Medvedev ; St. Petersburg State University, Russia

The paper describes an experience of creating a hardware implementation of a pairwise sequence alignment algorithm in a high-level hardware description language. The implementation is created to be run on an FPGA with a high latency interface to a PC (ethernet). Thus, a lot of control logic is implemented in hardware together with the main pipeline. We use a HaSCoL hardware description language for that purpose and discuss pros and cons of this approach compared to software implementation of the control logic on an embedded processor. We also discuss how the language helps to describe hardware and how it could help more as well.

Published in:

Software Engineering Conference in Russia (CEE-SECR), 2011 7th Central and Eastern European

Date of Conference:

Oct. 31 2011-Nov. 3 2011