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Traditional methods of performing worst-case DC or static analysis serves limited purposes for power delivery network (PDN) validation, especially when it comes to modeling chip-package-PCB coupling or resonance behavior. These methods do not consider the inductive and capacitive elements that dominate the chip and package interaction. They also fail to capture the impact of simultaneous switching current in creating local hot-spots and global voltage rail collapse. In this study, an analysis methodology that combines the use of both time and frequency domain techniques to model the impact of Ldi/dt noise and the coupling of chip-level switching current with chip-package impedance is presented. The outlined techniques were used on a design targeting high-speed signal processing applications to identify resonance behavior of chip-package PDN systems. Simulations were performed on various configurations of the design to ensure that the proposed design changes would correct the resonance and other PDN related issues. The analysis flow, information on the various data used, run-time and performance statistics, and the results from these experiments are presented.