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Thermal via structural design in three-dimensional integrated circuits

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3 Author(s)
Leslie Hwang ; Electrical and Computer Engineering, University of Illinois at Urbana-Champaign Coordinated Science Laboratory, Urbana, IL USA ; Kevin L. Lin ; Martin D. F. Wong

3D IC, a novel packaging technology, is heavily studied to realize improved performance with denser packaging and reduced wirelength. Despite numerous advantages, thermal management is the biggest bottleneck to realize device stacking technology. In this paper, we propose a thermal-aware physical design for three-dimensional integrated circuits (3D IC). We aim to mitigate localized hotspots to ensure functionality by adding thermal fin geometry to existing thermal through silicon via (TTSV). We analyze various ways to insert thermal fin for single TTSV as well as TTSV cluster designs with the goal of maximizing heat dissipation while minimizing the interference with routing and area consumption. An analytical model of a three-dimensional system is developed and a thermal resistance circuit is built for accurate and time-efficient 3D thermal analysis.

Published in:

Thirteenth International Symposium on Quality Electronic Design (ISQED)

Date of Conference:

19-21 March 2012