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A complete digital signal processing architecture for software defined radios (SDRs) has been developed for several NASA missions under the JHU/APL name Frontier Radio.1, 2 The design is completely integrated into a single field programmable gate array (FPGA), and includes all processing necessary to execute a variety of modulation and demodulation schemes, as well as abstract the radio hardware and control up to a human interface level. A balance in the inherent dichotomy between key mission requirements, low power and infinite flexibility, has been achieved with an eye towards FPGA and space flight qualified application specific integrated circuit (ASIC) commercial device trends. The Space Telecommunications Radio System (STRS) compliant modular design architecture allows for low cost reconfiguration, replacement, or addition of functionality. Trades made during the development process of this architecture are discussed: including different firmware development paths, FPGA integration vs. commercial device usage, and implementation of digital signal processing (DSP) mathematics. Several usage scenarios, STRS Waveforms, of the FPGA architecture are discussed together with tested performance metrics.