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Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers

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5 Author(s)
Hsiu-Ming Chang Chang ; Univ. of California, Santa Barbara, Santa Barbara, CA, USA ; Jiun-Lang Huang ; Ding-Ming Kwai ; Kwang-Ting Cheng
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This paper presents an error tolerance scheme for 3-D CMOS imagers that are constructed by stacking a pixel array of imager sensors, an analog-to-digital converter (ADC) array, and an image signal processor (ISP) array using microbumps (μbumps) and through silicon vias (TSVs). To deliver high-quality images in the presence of single or multiple μbump, ADC, or TSV failures, we propose to interleave the connections from pixels to ADCs and recover the corrupted data in the ISPs. Key design parameters, such as the interleaving stride and the grouping ratio are determined by analyzing the employed error correction algorithm. Architectural simulation results demonstrate that the error tolerance scheme enhances the effective yield of an exemplar 3-D imager from 44% to 97%.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:21 ,  Issue: 3 )