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A Fully Digital Delay Line Based GHz Range Multimode Transmitter Front-End in 65-nm CMOS

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5 Author(s)
Nuyts, P.A.J. ; Dept. of Electr. Eng. (ESAT), Katholieke Univ. Leuven, Leuven, Belgium ; Singerl, P. ; Dielacher, F. ; Reynaert, P.
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This paper presents a fully digital polar up-converter for wireless transmission in the GHz range. The system is designed to drive two class-E power amplifiers (PAs) with a power combiner. It uses baseband pulse width modulation (PWM) for the amplitude modulation (AM), whereas phase modulation (PM) is implemented by shifting the RF carrier in time. Both the PWM and the PM are implemented using asynchronous delay lines which allow time resolutions down to 10 ps without the need for any reference frequencies higher than the carrier frequency. The system supports a continuous range of carrier frequencies from 946 MHz up to 2.4 GHz. It also supports a continuous range of sampling frequencies, which allows trading off signal quality for PA efficiency. The modulator has been implemented in 65-nm low-power CMOS. Measurements using 64-QAM OFDM signals show error vector magnitude (EVM) values ranging from 1.90% (-34.4 dB) for 5-MHz bandwidth signals at 946 MHz to 6.08% (-24.3 dB) for 20-MHz bandwidth signals at 2.4 GHz.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:47 ,  Issue: 7 )

Date of Publication:

July 2012

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