We are currently experiencing intermittent issues impacting performance. We apologize for the inconvenience.
By Topic

FPGA implementation of 16 bit BBS and LFSR PN sequence generator: A comparative study

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Sewak, K. ; Dept. of ECE, Guru Ghasidas Vishwavidyalaya, Bilaspur, India ; Rajput, P. ; Panda, A.K.

The main purpose of this paper is to study the FPGA implementation of two 16 bit PN sequence generator namely Linear Feedback Shift Register (LFSR) and Blum-Blum-Shub (BBS). We have used FPGA to explain how FPGA's ease the hardware implementation part of communication systems. The logic of PN Sequence Generator presented here can be changed any time by changing the seed in LFSR or by changing the key used in BBS. The analysis is conceded out to find number of gates, memory and speed requirement in FPGA for the two methods. As Recently the field programmable gate arrays have enjoyed wide spread use due to several advantages related to relatively high gate density, short design cycle and low cost. The greatest advantage of FPGA's are flexibility that we reconfigured the design many times and check the results and verify it on-chip for comparing with others PN sequence generators.

Published in:

Electrical, Electronics and Computer Science (SCEECS), 2012 IEEE Students' Conference on

Date of Conference:

1-2 March 2012