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This paper focuses on stress generated in Si dies as a consequence of the interaction mechanism of the underfill material and microbumps in 3D stacked integrated circuits (ICs). The impact of the mechanism is simulated by means of finite element modeling (FEM) and verified by electrical measurements. Furthermore, a FEM study is employed in order to provide proposals for stress reduction in the active Si area due to stacking. In result, guidelines for the choice of underfill material and critical dimensional parameters of 3D stacks are pointed out.