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Hole Mobilities of \hbox {Si/Si}_{0.5}\hbox {Ge}_{0.5} Quantum-Well Transistor on SOI and Strained SOI

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11 Author(s)
Yu, W. ; Shanghai Inst. of Microsyst. & Inf. Technol., Shanghai, China ; Zhang, B. ; Zhao, Q.T. ; Buca, D.
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Hole mobilities of quantum-well p-MOSFETs on strained Si (sSi)/Si0.5Ge0.5/strained SOI (sSOI) and Si/Si0.5Ge0.5/SOI heterostructure substrates are investigated as a function of temperature. Ge interdiffusion during annealing in highly strained Si0.5Ge0.5 on SOI is reduced by the growth of Si0.5Ge0.5 layer on biaxially tensely strained SOI. As a result, the sSi/Si0.5Ge0.5/sSOI transistors showed significantly higher hole mobilities than the Si/Si0.5Ge0.5/SOI device at low temperatures.

Published in:

Electron Device Letters, IEEE  (Volume:33 ,  Issue: 6 )