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This paper presents an all-digital phase-locked loop (ADPLL) that features separate use of integer and fractional parts for the phase digitization in the feedback path. This separation simplifies the circuit implementation allowing reduced power consumption and silicon area. The proposed arrangement frees the ADPLL from potential metastability hazard during fine-tuning operation. Furthermore, it eliminates spurious tones associated with frequency reference retiming. In addition, the ADPLL employs an original frequency calibration technique that allows an extremely fine calibration resolution with minimized calibration time. Theoretical analysis is provided for both the architectural modification and frequency calibration technique. The ADPLL has been implemented in a 65-nm CMOS. Its simulation and measurement results are presented.