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Programming Time-Multiplexed Reconfigurable Hardware Using a Scalable Neuromorphic Compiler

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5 Author(s)
Minkovich, K. ; Dept. of Inf. & Syst. Sci., HRL Labs. LLC, Malibu, CA, USA ; Srinivasa, N. ; Cruz-Albrecht, J.M. ; Youngkwan Cho
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Scalability and connectivity are two key challenges in designing neuromorphic hardware that can match biological levels. In this paper, we describe a neuromorphic system architecture design that addresses an approach to meet these challenges using traditional complementary metal-oxide-semiconductor (CMOS) hardware. A key requirement in realizing such neural architectures in hardware is the ability to automatically configure the hardware to emulate any neural architecture or model. The focus for this paper is to describe the details of such a programmable front-end. This programmable front-end is composed of a neuromorphic compiler and a digital memory, and is designed based on the concept of synaptic time-multiplexing (STM). The neuromorphic compiler automatically translates any given neural architecture to hardware switch states and these states are stored in digital memory to enable desired neural architectures. STM enables our proposed architecture to address scalability and connectivity using traditional CMOS hardware. We describe the details of the proposed design and the programmable front-end, and provide examples to illustrate its capabilities. We also provide perspectives for future extensions and potential applications.

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Neural Networks and Learning Systems, IEEE Transactions on  (Volume:23 ,  Issue: 6 )