By Topic

Model-free estimation of defect clustering in integrated circuit fabrication

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Friedman, D.J. ; Integral Inc., Cambridge, MA, USA ; Hansen, M.H. ; Nair, V.N. ; James, D.A.

This paper describes a model-free method for estimating some yield metrics that are used to track integrated circuit fabrication processes. Our method uses binary probe test data at the wafer level to estimate the size, shape and location of large-area defects or clusters of defective chips. Unlike previous methods in the yield modeling literature, our approach makes extensive use of the location of failing chips to directly identify clusters. An important by product of this analysis is a decomposition of wafer yield that attributes defective chips to either large- or small-area defects. Simulation studies show that our procedure is superior to the time-honored windowing technique for achieving a similar breakdown. In addition, by directly estimating defect clusters, we can provide engineers with a greater understanding of the manufacturing process. It has been our experience that routine identification of the spatial signatures of clustered defects and associated root-cause analysis is a cost-effective approach to yield and process improvement

Published in:

Semiconductor Manufacturing, IEEE Transactions on  (Volume:10 ,  Issue: 3 )