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Fast/area efficient 8-bit A/D and D/A designs in 0.8 μm cmos technology using layout generators

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3 Author(s)
V. G. Balakrishan ; Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA ; S. Ramaswamy ; R. E. Siferd

High performance 8-bit analog-to-digital (A/D) and digital-to-analog (D/A) converters are presented here. To realize the DAC, the advantages of voltage scaling and charge scaling techniques have been combined. For the ADC, a two step “ripple through” A/D architecture which achieves high conversion speeds and area efficiency is presented. Both the A/D and D/A designs were realized using the Mentor Graphics Generator Design Tools (GDT)

Published in:

Aerospace and Electronics Conference, 1997. NAECON 1997., Proceedings of the IEEE 1997 National  (Volume:1 )

Date of Conference:

14-18 Jul 1997