A fast and low cost architecture developed in FPGAs for solving systems of linear equations

This paper presents a low cost architecture for the solution of linear equations based on the Gaussian Elimination Method using a reconfigurable system based on FPGA. This architecture can handle single data precision that follows the IEEE 754 floating point standard. The implementation takes advantage of both the internal memory and the DSP blocks (available in the Virtex-5 FPGA). The architectural approach is composed of four modules and one specific unit (namely, Change Row Module, Pivo Module, FB Module, Normalization Module and finally the Gaussian Elimination Controller Unit). This structure can be combined with other smaller arithmetic units in order to maintain the accuracy of the results without the need to internally normalize and de-normalize the floatingpoint data. Also, a special Memory Access Unit was implemented in order to deal with the writing/reading operations to/from the internal RAM. The resource consumption of the implementation (specially the internal RAM memory blocks that are used) points out several improvements when compared to previous work of the authors and other more elaborated architectures whose implementations are significantly more complex and, thus, unsuitable for low cost applications.