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FastTrack: Toward Nanoscale Fault Masking With High Performance

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5 Author(s)
Khan, M.M.U. ; Univ. of Massachusetts, Amherst, MA, USA ; Narayanan, P. ; Joshi, P. ; Panchapakeshan, P.
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High defect rates are associated with novel nanodevice-based systems owing to unconventional and self-assembly-based manufacturing processes. Furthermore, in emerging nanosystems, fault mechanisms and distributions may be very different from CMOS due to unique physical layer aspects, and emerging circuits and logic styles. Development of analytical fault models for nanosystems is necessary to explore the design of novel fault tolerance schemes that could be more effective than conventional schemes. In this paper, we first develop a detailed analytical fault model for the nanoscale application specific integrated circuits (NASIC) computing fabric and show that the probability of 0-to-1 faults is much higher than of 1-to-0 faults. We then show that in fabrics with unequal fault probabilities, using biased voting schemes, as opposed to conventional majority voting, could provide better yield. However, due to the high defect rates, voting will need to be combined with more fine-grained structural redundancy for acceptable yield. This entails degradation in performance (operating frequency) due to an increase in circuit fan-in and fan-out. We, therefore, introduce a new class of redundancy schemes called FastTrack that combine nonuniform structural redundancy with uniquely biased nanoscale voters to achieve greater yield without a commensurate loss in performance. A variety of such techniques are employed on a wire streaming processor (WISP-0) implemented on the NASIC fabric. We show that FastTrack schemes can provide 23% higher effective yield than conventional redundancy schemes even at 10% defect rates along with 79% lesser performance degradation.

Published in:

Nanotechnology, IEEE Transactions on  (Volume:11 ,  Issue: 4 )