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Recently, several advanced phase-locked loop (PLL) techniques have been proposed for single-phase applications. Among these, the Park-PLL and the second-order-generalized-integrator-based PLL are very attractive, owing to their simple digital implementation, low computational burden, and desired performance under frequency-varying and harmonically distorted grid conditions. Despite the wide acceptance and use of these two advanced PLLs, no comprehensive design guidelines to fine-tune their parameters have been reported yet. Through a detailed mathematical analysis, it is shown that these two PLL structures are equivalent to each other, from the control point of view. Then, a linearized model is developed which is valid for both PLLs. The derived model significantly simplifies the stability analysis and the parameter design. To fine-tune the PLL parameters, a systematic design approach is suggested afterward, which guarantees a fast dynamic response, a high disturbance rejection ability, and a robust performance. Finally, the simulation and experimental results are presented to support the theoretical analysis.