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Comparison of Preemption Schemes for Partially Reconfigurable FPGAs

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5 Author(s)
Krzysztof Jozwik ; Graduate School of Information Science, Nagoya University ; Hiroyuki Tomiyama ; Masato Edahiro ; Shinya Honda
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Preemption techniques for hardware (HW) tasks have been studied in order to improve system responsiveness at the task level and improve utilization of the FPGA area. This letter presents a fair comparison of existing state-of-the-art preemption approaches from the point of view of their capabilities and limitations as well as impact on static and dynamic properties of the task. In comparison, we use a set of cryptographic, image, and audio processing HW tasks and perform tests on a common platform based on a Virtex-4 FPGA from Xilinx. Furthermore, we propose the preemption as a method which can effectively increase FPGA utilization in case of HW tasks used as CPU accelerators in systems with memory protection and virtualization.

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IEEE Embedded Systems Letters  (Volume:4 ,  Issue: 2 )