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Design and implementation of a high performance multiplier using HDL

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2 Author(s)
Aparna, P.R. ; Dept. of ECE, Lourde Matha Coll. of Sci. & Technol., Kuttichal, India ; Thomas, N.

This paper presents an area efficient implementation of a high performance parallel multiplier. Radix-4 Booth multiplier with 3:2 compressors and Radix-8 Booth multiplier with 4:2 compressors are presented here. The design is structured for m × n multiplication where m and n can reach up to 126 bits. Carry Lookahead Adder is used as the final adder to enhance the speed of operation. Finally the performance improvement of the proposed multipliers is validated by implementing a higher order FIR filter. The design entry is done in VHDL and simulated using ModelSim SE 6.4 design suite from Mentor Graphics. It is then synthesized and implemented using Xilinx ISE 9.2i targeted towards Spartan 3 FPGA.

Published in:

Computing, Communication and Applications (ICCCA), 2012 International Conference on

Date of Conference:

22-24 Feb. 2012

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