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Area and power efficient VLSI architecture for DCT

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2 Author(s)

The objective of this paper is to design a VLSI based Discrete Cosine Transform (DCT) which is widely used in image and video compression, Video coding systems. This proposed design comprised of Distributed Arithmetic (DA) based VLSI architecture of DCT for reducing the power consumption. The circuit is designed with low power consumption techniques by using low power logical elements which can depend upon the system clock; this technique reduces the glitches and unwanted delays produced in design. The proposed system consists of two modules where the first module is basically the design of 1D Discrete cosine transform for existing method and 1D Discrete Cosine Transform using distributed architecture for proposed method. The simulation is performed on Modelsim6.5a simulator and power consumption can be calculated by using ALTERA power estimation tool.

Published in:

Computing, Communication and Applications (ICCCA), 2012 International Conference on

Date of Conference:

22-24 Feb. 2012